The present invention relates to a semiconductor device, and more particularly, to a semiconductor device capable of preventing a passing gate effect from being generated and a method of fabricating the same.
As the chip size of semiconductor memory, and more particularly dynamic random access memories (DRAM), is increased, the number of chips per wafer is reduced and thus productivity of the device is lowered. Therefore, there are endeavors to reduce a cell area by changing a cell layout to integrate more memory cells on a wafer. As a result, the cell layout is changed from the 8F2 structure to 6F2 structure.
FIG. 1 is a view illustrating a layout of a semiconductor device having the 6F2 layout structure in the related art.
In the semiconductor device having the 6F2 layout structure, an active region is obliquely defined in a semiconductor substrate, and a gate and a bit line are formed in a line shape to orthogonally cross each other on the substrate in which the active region is defined. Two line shaped buried gates BG are disposed to pass through each active region, and the bit line BL is disposed to orthogonally cross the buried gate BG and to pass through a central portion of the active region. A bit line contact plug is formed in each active region between the two gates BG, and a storage node contact plug is formed in portions of the active region at outer sides of the two buried gates. All of the storage node contact plug and the bit line contact plug are disposed in the active region in the 6F2 layout structure, and thus the integration degree is increased compared with an 8F2 structure.
Since each gate is formed in the line shape, a portion of the gate is disposed in the active region to be used for forming a channel and a portion of the gate is formed in a device isolation region to pass by the active region.
The gate that passes through several active regions may be referred to as a passing gate. A passing gate may cause a passing gate effect in which a gate passes through active regions that are turned on and turned off, and the turned on conditions influence a voltage of the turned off regions by lowering the turn-on voltage for influenced regions.
Further, a passing gate may cause a “0” failure in a word line disturb (DIST) test.